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Axis Dumps

statement-primarily based Emulation Methodology | ANVE Cheatsheet and PDF Download

by way of Steven Wang, Axis SystemsSunnyvale, California u . s . a .

summary :Many americans are predicting that assertions should be the next massive breakthrough to permit engineers to continue to design and assess better and more complex designs. assertion-based mostly methodologies deliver much-needed structure to the latest set of ad-hoc testbench and monitoring innovations used via most projects for simulation, in addition to enable more widespread adoption of emerging formal and semi-formal verification technologies.

during this paper, Axis will talk about the brand new phrases and definitions linked to assertions, as neatly because the proposed dissimilar methodologies. The dialogue will cowl terms, reminiscent of assertion, Property, Constraint, experience, Procedural fact, Declarative statement, and Formal Property Language. The paper will further explore a few statement methodologies, comparable to Open Verification Library (OVL), SystemVerilog, Open Vera Assertions (OVA), Sugar, and zero-In CheckerWare, and clarify the way to examine which formula is premiere for a selected condition. one of the most merits of fact-primarily based methodology is its application in an emulation environment. Emulation has lengthy suffered from bad visibility and the stream to assertions drastically improves emulation debug. This paper will additionally discuss an interrupt-driven event-primarily based emulation technology that permits access to behavioral code, comparable to $reveal or PLI, as assertion screw ups are detected in emulation.

The Verification ChallengeAs brand new designs push previous 1M gates and move toward 10M gates, engineers require new equipment and methodologies to examine these contraptions. unluckily, some engineers predict to verify these chips the usage of the identical waveform dumps, adhoc testbench code with $monitor statements, and scripts with log file greps to display screen simulation outcomes.

What is needed is a typical methodology on the way to propel the use of assertions across a wide selection of tools ranging from formal verification to good judgment simulation to emulation. This regular methodology will supply multiplied automation and allow the total improvement of the write-as soon as characteristic of assertions.

Axis is participating in making this vision a reality by way of teaching engineers on the price of assertionbased verification and making bound statement-based mostly methodologies work neatly with its simulation, simulation acceleration, and emulation items. The aggregate of assertions with the generalpurpose ReConfigurable Computing (RCC) verification platform for simulation, simulation acceleration, and emulation will supply users with the crucial efficiency and debugging to meet verification requirements for the subsequent generation of designs.

Introduction to Assertions

Assertions document the dressmaker's assumptions and the residences of the design. they're a magnificent tool to crosscheck the design's precise versus meant conduct. they are additionally valuable to verification and system engineers to formally specify the intended behavior of the device and to make sure it is behaving based on specification. these days, a good deal has been written about assertions, and besides the fact that the conception has existed for years, there continues to be a whole lot confusion over assertions. earlier than entering into the particulars of how assertions are specified and carried out, it's advantageous to seem at the motivation at the back of why assertions are so vital.

Assertions provide a typical format for dissimilar tools. with out an agreed-on formula of specifying assertions, there is no probability to automate actions, akin to purposeful coverage metrics, error reporting, and severity levels. a typical statement methodology lends itself to extended automation in each formal verification and simulation. Assertions can additionally benefit from a "write-once, run-any place" characteristic. as soon as inserted right into a design, they can also be used via many tools and are quite transportable for design reuse.

Assertions are improved than a paper test plan. Verification includes deriving a list of facets to be proven from the design specification. Most initiatives write a test plan that dictates how the aspects of the design are to be demonstrated. These points are then documented, and a testcase is developed to verify every characteristic. Testcases constantly take the type of a testbench with a purpose to cause the preferred feature to be exercised. This directed method is frequently augmented with random checking out. Assertions aid to automate the guide manner of operating a testcase: visually verifying the verify has covered the characteristic and including the check to the regression suite. devoid of the usage of assertions, there's commonly no way to guarantee that the testcase nonetheless workout routines the characteristic as the design evolves. Assertions supply a mechanism to measure practical coverage and quantify look at various outcomes.

Assertions ease debugging and in the reduction of simulation time. one of the most leading motivations for assertions is reduced debugging time. for the reason that assertions are a white-field verification approach, they supply improved visibility and controllability of the design under verify. Assertions will observe design error as quickly as they turn up with out awaiting the effects to be propagated to the machine or gadget boundaries. Having an immediate indication of a problem can shop hours of making an attempt to look backward to get to the basis reason behind the difficulty. using assertions has been pronounced to in the reduction of debugging time with the aid of as much as 50% [1]. Assertions can also store simulation time given that they can terminate a simulation when a deadly error occurs. A runaway or meaningless simulation can waste beneficial simulation time if it happens all through an overnight regression run when more checks may well be given a chance to run.

Assertions assess interfaces between blocks. all through integration phases, assertions act as watchdogs on the module or block interface boundaries making certain each and every block obeys the agreed-on protocol. This may also be critical since it's feasible for a testcase to circulate, based on the facts followed on the chip or system boundaries, even when there's a violation of a protocol inside the design. Assertions support get rid of such situations.

Assertions are a fine RTL coding apply. Assertions are way more valuable than comments by myself within the design. well-commented code makes it more straightforward to maintain and to bear in mind the supposed performance. Assertions go one step further by way of documenting exactly what the code is expected to do in a means that can also be Checked using equipment instead of an individual analyzing the feedback and attempting to have in mind if the code is working as it should be. Assertions are also a good way to sanitize the code before determine-in. equipment can examine a design file and its assertions and point out viable problem areas. within the identical way, a lint application checks for blunders in the code's syntax and constitution, assertions may also be used to determine for errors in the design's habits. Assertions supply many advantages to system-level engineers, design engineers doing RTL coding, and verification engineers. each group brings distinct expertise concerning the design and its operation, but a typical assertion methodology makes it possible for all parties to improvement.

fact Definitions

To take note more particulars of an fact-based methodology, a common set of definitions is introduced.

Property: A well-known behavioral attribute used to symbolize a design. homes will also be excessive-stage attributes, reminiscent of traits of incoming and outgoing networking packets or low-stage attributes involving the state encoding of a finite state computing device (FSM).

adventure: An occurrence of a attractive conduct. staring at activities is required as a part of verification to ensure completeness. Measuring the prevalence of events results in quantitative records about specific corner instances and shows that other residences of the design have been proven. facts about activities result in functional coverage metrics.

assertion: An statement is an announcement about a selected property it is anticipated to be authentic for the design. Assertions are most frequently used to trap undesirable behavior. Assertions are checkers and monitors used to enforce rules and assumptions about the design.

Static: An event or statement that is true for all time or is only checked at a selected illustration of time. No abilities of outdated background of the design state is required.

Temporal: An adventure or statement that spans a sequence of time. background is required to music the sequence over time.

Procedural assertion: An fact described within the context of an executing process or set of sequential statements, akin to a VHDL method or a Verilog all the time block. The assertion will be evaluated in accordance with the path taken throughout the set of sequential statements.

Declarative assertion: An statement that exists within the structural context of the design. it's evaluated along with all of the different structural elements within the design, for example, a module that takes the type of a structural instantiation.

typical Expression: a regular expression is a method to categorical how a laptop application should search for a targeted pattern and how to react when matching patterns are found. a common use of commonplace expressions is found in the UNIX grep device. Specification of properties is readily achieved the usage of usual expressions. This explains why languages equivalent to PERL are used in design verification applications.

Property Language, Declarative Language, fact Language, Formal Property Language: All of those languages are used interchangeably to explain a language that may also be used to describe high-degree design standards, houses, routine, and assertions. These languages are designed to provide a concise layout for complex temporal sequences and general expressions.

fact processes

five procedures to assertions have been described within the literature:

  • Declarative Assertions the use of a library of Verilog video display modules
  • Procedural Assertions the usage of a Verilog assert construct
  • Formal property languages
  • Pseudo-remark directives
  • put up-processing simulation history
  • As of this writing, quite a few theories about which methodology is top-rated for assertions are fragmented. The aim here is not to advertise one versus one other, but to introduce each and every and listing one of the commonly documented professionals and cons. The examples used are not meant to be comprehensive, however they do cover one of the extra widely discussed methods.

    Declarative Assertions

    essentially the most regular methodology for assertions today uses the declarative assertions within the Open Verification Library (OVL), which is freely purchasable at www.verificationlib.org. OVL is an statement display screen library of Verilog modules that will also be with no trouble instantiated right into a design. OVL offers a constant method to specify static and temporal assertions in RTL code. OVL provides a unified message reporting mechanism that may also be quite simply customized for certain tasks by means of changing little or no code. It also offers a simple method to allow and disable assertions all through simulation. OVL also offers a consistent severity degree scheme that will also be used to cease simulation on fatal blunders. Work on OVL is continuing with approximately two new releases per year. OVL will continue to conform as related requirements stabilize. OVL is awfully handy to make use of and is a great first step in getting started with assertions. it's obtainable now and has been proven and used on many initiatives. Its open supply layout makes it attractive for the reason that it can also be customized for each software. considering OVL uses a library of modules, the assertions should be instantiated into the design. The one means it does not currently have is procedural assertions, which can be from time to time known as in-context assertions.

    Procedural Assertions

    as an alternative of instantiating a module from a library, from time to time it's greater convenient to specify assertions the use of procedural statements. Such is the case with the new assert construct that is part of the SystemVerilog 3.0 specification authorised with the aid of Accellera (work is carrying on with in SystemVerilog three.1). Procedural assertions are effective in the context of a Verilog always block with procedural code, reminiscent of a case observation or an if-then-else block. Procedural assertions can also be inserted into the code, reckoning on which department has been taken. This permits the assertions to be active all through the context by which they are essential. each declarative and procedural assertions are first rate the right way to seize design intent throughout the RTL coding manner. if they aren't captured during this part, the advantage is probably lost on account that it is not likely anybody will go lower back to insert these assertions.

    Formal Property Language

    The next method used for assertions employs a proper property language. These languages are constructed for the aim of specifying design properties with minimum effort. they're very effective in creating advanced temporal expressions, and that they additionally make use of common expressions to enable advanced behavior to be distinct with very little code. These languages have existed for decades, but have not been used in mainstream design. existing examples are Sugar, which is being used by way of the Accellera formal verification committee, and the Open Vera Assertions (OVA), which is being used with the aid of Synopsys for formal verification tools, as well as in the VCS good judgment simulator. Formal property languages are advantageous right through all phases of the task and at all tiers of design. gadget architects can use these languages to specify high-degree properties of the design. They can also be used by way of verification IP based mostly SoC Design 2002 - October 30-31, 2002 4 engineers to perform black-field verification with out figuring out all the details of the design and by way of RTL designers to specify low-level assertions in regards to the code. One aspect that has previously been difficult about assertions is the relationship between the formal property language and procedural assertions, such as the SystemVerilog assert language assemble. definitely, there's lots overlap on the grounds that each will also be used to specify assertions. The formal property language is extra regular purpose, not tied to any certain language concerns of Verilog or VHDL. Over time the syntax used to specify properties will converge in order that a single syntax can work for each a formal property language and HDL language extensions. If here is now not viable due to constraints of the Verilog namespace, at the least the syntax should still be very shut. at the moment, equipment using a proper property language for assertions constantly put them into a separate file so formal equipment and simulators can system them one by one.

    Pseudo-remark Directives

    one other method that has been taken to specify assertions is using pseudo-feedback. via embedding assertions in comments, they will also be put at once into the RTL code and may not interfere with the Verilog syntax or require any changes to the simulator. Formal verification tools can examine the comments the use of a unique parser. moreover formal strategies, these tools can also output a Verilog RTL equal for each and every fact that allows the statement to be simulated and flagged in a standard good judgment simulator. This instrumentation technique is helpful for the reason that it will probably automatically collect purposeful insurance metrics about movements and assertions all through a simulation run, create a database of pastime, and display the exercise in a concise format for users. facts from dissimilar simulations may be merged to kind a complete photo of practical coverage. The methodology is akin to the instrumentation procedure regular in code insurance; 0-In Design Automation is working during this area.

    submit-Processing Simulation history

    thus far, the entire methods described have finished fact checking during simulation. a different approach is to determine for assertions after a simulation look at various is complete. within the identical means engineers use waveform dumps to debug an issue after the simulation is finished, they could verify for hobbies and assertions. TransEDA has developed a tool that may read a waveform file in VCD or FSDB structure, read a collection of assertions distinctive in PERL or Sugar, and provide tips about the assertions during the simulation run. this system does not require any changes to the simulator, any language extensions, or any alterations to the design info. reckoning on the variety of alerts essential and the length of the simulation, large waveform data may well be required.

    know-how and dreams for statement-based mostly Methodologies

    An method of statement-primarily based methodology is ReConfigurable Computing (RCC) technology through Axis methods. RCC shortens lengthy simulation instances and raises simulation productivity through offering advanced debugging points, reminiscent of simulation sizzling swap and VCD-on-Demand, that enable engineers to straight away find complications. Enabling a consistent methodology all the way through simulation, acceleration, and emulation, RCC provides the maximum simulation efficiency and the means to run behavioral code, such as $display and PLI.

    As designs get better and greater, they are going to require some sort of acceleration and/or emulation to achieve verification dreams. by way of enabling sooner simulation that works neatly with assertions, clients can leverage both of those rising applied sciences to meet project goals. traditionally, the cost of emulation become uncooked efficiency. Emulation users have suffered vastly from terrible visibility all the way through emulation. in contrast to simulation, emulation doesn't allow testbench and displays to document endeavor in the emulator. Assertions are a way to supply this visibility. a good implementation of assertions maintains the efficiency value of emulation and gives the visibility to significantly increase emulation debugging. definitely, operating quicker is advantageous, but when engineers need to eliminate assertions all over emulation, all of the aforementioned benefits of assertions are fully misplaced.

    assertion Processor

    Assertions can be decomposed into two elements: detection and failure processing. assertion detection is accomplished the usage of state machines. all the temporal expressions which are used to write an assertion can also be implemented in the sort of an RTL state laptop. by using definition, RCC can run all fact detection in RCC hardware at hardware pace. corresponding to a microprocessor interrupt, statement Processor receives interrupts when assertions fail and activates a software provider hobbies that runs on the pc and has entry to behavioral code, corresponding to $screen or PLI. statement Processor permits engineers to keep using assertions from simulation to simulation acceleration and into emulation with out being compelled to eradicate them or execute fact detection in software simulation. Assertions become a effective debugging device within the historically complicated-to-debug emulation environment.

    The interrupt-driven implementation of assertion Processor is more productive than polling for fact violations from a utility testbench and does not influence emulation velocity when there are not any fact violations. Polling requires many bits interior the emulator to be examine each clock cycle. If the design incorporates 10,000 assertions, then an equal number of bits ought to be study every clock cycle. Then, the bits have to be examined to discover if any assertions had been brought on, and if so, the acceptable statement processing code is executed. trying out by using Axis has shown polling to be four instances slower than an interrupt-pushed implementation. The interrupt-driven architecture provides the necessary visibility and the efficiency of assertion detection in hardware. The introduced knowledge of the RCC engine is its adventure-based mostly algorithm. assertion Processor accurately handles assertions that are not sampled on clock cycle boundaries because of the experience-based algorithm of RCC. Cycle-based mostly algorithms and polling on clock cycle boundaries can not deal with these types of assertions.

    For fatal assertions, handle is required to cease the simulation in its place of losing simulation cycles. This will also be completed from the software carrier hobbies the usage of common Verilog commands, equivalent to $finish.

    a further characteristic of fact Processor is the capacity to configure it to perform simulation hot swap and stop during fact processing. now not most effective does swap and stop enable behavioral code to be run, however gives a user supply-degree debugging and entire access to the entire signals of the design. Some engineers opt to use this interactive style of debugging as a substitute of exiting the simulation and the use of submit-processing debugging equipment. After debugging is comprehensive, the person has the alternative to exit, to proceed to run in the utility simulator, or to use simulation hot swap to load the simulation lower back into the RCC engine and continue.

    for instance of the usage of statement Processor, agree with the assertion shown in determine 1. This assertion will also be coded the use of the assert_change module from OVL, as proven in determine 2. To permit OVL to map to RCC to get the benefits of the $reveal statement reporting, the ovl_error project in ovl_task.h is personalized. When the fact fails, the display_task should be achieved in application on the computer so the $monitor is seen and entered into the simulation log file as common. A diagram displaying how assertion-processing works is proven in determine three.

    clients obtain the optimum debugging productiveness by means of combining fact Processor with VCD-on- Demand (VoD) to generate waveform assistance. VCD-on-Demand (VoD) alleviates the boundaries associated with tremendous waveform data and the battle to make a decision when to dump and what to dump into waveform info. users can run devoid of specifying any dumping, and after the run is complete, they could go lower back to provide a waveform file for any favored window of simulation time and any scope of the design. Assertions pinpoint design blunders, and VoD provides the top of the line method to provide waveforms beginning on the element of statement failure and working returned to the root cause of the difficulty with out re-working simulation. A diagram showing the debugging circulate with VoD is proven in determine four.

    Axis is currently working with dissimilar assertion methodologies to ensure that they run smartly with Axis items, proposing the highest viable efficiency and debugging efficiency. particulars of selected assertion methodologies and associated design flows will continue to be documented in white papers and utility notes for clients in the hunt for the maximum efficiency verification platform combined with the existing statement-primarily based design and verification techniques.

    abstract

    assertion-based verification methodologies are the next breakthrough in design verification. When this methodology is combined with a high-performance verification platform, design teams can meet the challenges of the subsequent technology of complexity. An introduction to assertions has been provided, and the merits of such methodologies were applied to accepted logic simulation, in addition to to the certain RCC verification platform from Axis. a methodology has been described that leverages the rising set of formal verification tools, as well because the high-efficiency simulation equipment from Axis. statement count in latest ASIC designs usually tiers from 1,000 to 10,000 and incurs a ten to fifteen percent simulation efficiency penalty. With RCC know-how and statement Processor, fact detection executes in parallel with the design, and assertions incur no simulation performance overhead. by way of accelerating the design and the statement detection, users get the maximum degree of simulation performance whereas maintaining the increased observability offered by means of assertions with no exchange in design move. efficient assertion processing that uses an interrupt-driven implementation additionally keeps high efficiency when assertions fail.

    by using featuring the only universal goal platform that may accelerate assertions of many varieties, Axis is main the manner in promotion the write-as soon as, runanywhere characteristic of assertions and enabling assertions to be adopted all over all phases of the design cycle. Axis is the technology leader in IP primarily based SoC Design 2002 - October 30-31, 2002 6 simulation productiveness with its statement Processor, VCD-on-Demand, and simulation sizzling swap for superior simulation manage and visibility. Axis is presenting an open gadget and is working to help rising statement standards and methodologies and will proceed to and promote using assertions as requisites emerge and methodologies evolve.

    References:[1] T. Fitzpatrick, H. Foster, E. Marschner, P. Narain, "Introduction to Accellera's assertion efforts", EEdesign, June 2, 2002[2] Synopsys, Inc., "fact-based mostly Verification", may also 2002[3] H. Foster, "enhancing Verification via Property Specification", D&R business Articles[4] J. Emmitt, "Verifying complicated SoCs with OVL", electronic Engineering Design, January 28, 2002[5] 0-In Design Automation, Inc., "Black & White statement-based Verification move", The Verification video display, may 2002[6] L. Bening, H. Foster, concepts of Verifiable RTL Design, Kluwer tutorial Publishers, 2001[7] J. Bergeron, Writing Testbenches functional Verification of HDL models, Kluwer academic Publishers, 2000

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